TY - GEN
T1 - Deep Neural Network Model and FPGA Accelerator Co-Design
T2 - 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018
AU - Hao, Cong
AU - Chen, Deming
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/12/5
Y1 - 2018/12/5
N2 - With an explosive growth of various neural network algorithms, their high performance implementations on hardware platforms, such as GPUs and FPGAs, are becoming critical as well. Compared to widely used GPUs, FPGAs are considered to be harder for design and optimization even with the help of High Level Synthesis (HLS) tools. However, recent studies have shown that FPGAs can outperform GPUs in speed and power/energy efficiency; both factors are important in machine learning applications. In this paper, we will discuss a simultaneous DNN and hardware accelerator co-design method to push the DNN performance on FPGAs. We first summarize existing techniques and results along this direction, and then propose new ideas to further improve DNN development productivity and design quality. Finally we discuss the challenges we would face and propose some potential solutions.
AB - With an explosive growth of various neural network algorithms, their high performance implementations on hardware platforms, such as GPUs and FPGAs, are becoming critical as well. Compared to widely used GPUs, FPGAs are considered to be harder for design and optimization even with the help of High Level Synthesis (HLS) tools. However, recent studies have shown that FPGAs can outperform GPUs in speed and power/energy efficiency; both factors are important in machine learning applications. In this paper, we will discuss a simultaneous DNN and hardware accelerator co-design method to push the DNN performance on FPGAs. We first summarize existing techniques and results along this direction, and then propose new ideas to further improve DNN development productivity and design quality. Finally we discuss the challenges we would face and propose some potential solutions.
UR - http://www.scopus.com/inward/record.url?scp=85060271935&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85060271935&partnerID=8YFLogxK
U2 - 10.1109/ICSICT.2018.8564956
DO - 10.1109/ICSICT.2018.8564956
M3 - Conference contribution
AN - SCOPUS:85060271935
T3 - 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings
BT - 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings
A2 - Tang, Ting-Ao
A2 - Ye, Fan
A2 - Jiang, Yu-Long
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 31 October 2018 through 3 November 2018
ER -