@inproceedings{c0073534eaf9410ab041b4dd391a7490,
title = "DDBDD: Delay-driven BDD synthesis for FPGAs",
abstract = "In this paper, we target FPGA performance optimization using a novel BDD (binary decision graph)-based synthesis approach. Most of previous works have focused on BDD size reduction during logic synthesis. In this work, we concentrate on delay reduction and conclude that there is a large optimization margin through BDD synthesis for FPGA performance optimization. Our contributions are threefold: (1) we propose a gain-based clustering and partial collapsing algorithm to prepare the initial design for BDD synthesis for better delay; (2) we use a technique named linear expansion for BDD decomposition, which in turn enables a dynamic programming algorithm to efficiently search through the optimization space for the BDD of each node in the clustered circuit; (3) we consider special decomposition scenarios coupled with linear expansion for further improvement on quality of results. Experimental results show that we can achieve a 95% gain in terms of network depths, and a 20% gain in terms of routed delay, with a 22% area overhead on average compared to a previous state-of-art BDD-based FPGA synthesis tool, BDS-pga.",
keywords = "Binary decision diagrams, FPGA technology mapping, Linear expansion",
author = "Lei Cheng and Deming Chen and Wong, {Martin D.F.}",
note = "Copyright: Copyright 2011 Elsevier B.V., All rights reserved.; 2007 44th ACM/IEEE Design Automation Conference, DAC'07 ; Conference date: 04-06-2007 Through 08-06-2007",
year = "2007",
doi = "10.1145/1278480.1278705",
language = "English (US)",
isbn = "1595936270",
series = "Proceedings - Design Automation Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "910--915",
booktitle = "2007 44th ACM/IEEE Design Automation Conference, DAC'07",
address = "United States",
}