A process architecture to support VLSI mask checking is described. Rather than recast the entire verification task in hardware, the authors identify primitives around which geometry checking tools can be built, and accelerate these primitives. The architecture is based on a restructuring of classical scanline-sweep methods for direct hardware interpretation. Boolean operations and region numbering are supported for masks with restricted oblique geometry. Simulation benchmarks suggest practical speedups are attainable.
|Original language||English (US)|
|Title of host publication||Unknown Host Publication Title|
|Number of pages||4|
|State||Published - Dec 1 1986|
ASJC Scopus subject areas