@inproceedings{b1ca6e6b153042f8bbe4e3bf657b6a69,
title = "Data layout transformation exploiting memory-level parallelism in structured grid many-core applications",
abstract = "We present automatic data layout transformation as an effective compiler performance optimization for memory-bound structured grid applications. Structured grid applications include stencil codes and other code structures using a dense, regular grid as the primary data structure. Fluid dynamics and heat distribution, which both solve partial differential equations on a discretized representation of space, are representative of many important structured grid applications. Using the information available through variable-length array syntax, standardized in C99 and other modern languages, we have enabled automatic data layout transformations for structured grid codes with dynamically allocated arrays. We also present how a tool can guide these transformations to statically choose a good layout given a model of the memory system, using a modern GPU as an example. A transformed layout that distributes concurrent memory requests among parallel memory system components provides substantial speedup for structured grid applications by improving their achieved memory-level parallelism. Even with the overhead of more complex address calculations, we observe up to 560% performance increases over the language-defined layout, and a 7% performance gain in the worst case, in which the language-defined layout and access pattern is already well-vectorizable by the underlying hardware.",
keywords = "GPU, data layout transformation, parallel programming",
author = "Sung, {I. Jui} and Stratton, {John A.} and Hwu, {Wen Mei W.}",
year = "2010",
month = jan,
day = "1",
doi = "10.1145/1854273.1854336",
language = "English (US)",
isbn = "9781450301787",
series = "Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "513--522",
booktitle = "PACT'10 - Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques",
address = "United States",
}