Data access microarchitectures for superscalar processors with compiler-assisted data prefetching

William Y. Chen, Scott A. Mahlke, Pohua P. Chang, Wen Mei W. Hwu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The performance of superscrdar processors is more sensitive to the memory system delay than their single-issue predecessors. This paper examines alternative data access microarchitectures that effectively support compilerassisted data prefetching in superscalar processors. In particular, a prefetch buffer is shown to be more effective than increasing the cache dimension in solving the cache pollution problem. All in all, we show that a small data cache with compiler-assisted data prefetching can achieve a performance level close to that of an ideal cache.

Original languageEnglish (US)
Title of host publicationMICRO 1991 - Proceedings of the 24th Annual International Symposium on Microarchitecture
PublisherIEEE Computer Society
Pages69-73
Number of pages5
ISBN (Print)0897914600, 9780897914604
DOIs
StatePublished - Sep 1 1991
Event24th Annual International Symposium on Microarchitecture, MICRO 1991 - Albuquerque, United States
Duration: Nov 18 1991Nov 20 1991

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
ISSN (Print)1072-4451

Other

Other24th Annual International Symposium on Microarchitecture, MICRO 1991
CountryUnited States
CityAlbuquerque
Period11/18/9111/20/91

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ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Chen, W. Y., Mahlke, S. A., Chang, P. P., & Hwu, W. M. W. (1991). Data access microarchitectures for superscalar processors with compiler-assisted data prefetching. In MICRO 1991 - Proceedings of the 24th Annual International Symposium on Microarchitecture (pp. 69-73). (Proceedings of the Annual International Symposium on Microarchitecture, MICRO). IEEE Computer Society. https://doi.org/10.1145/123465.123478