With IC technology scaling down to nanometer sizes, the higher working frequency and smaller geometry drive the reliability of signal interconnects to be a critical challenge in VLSI design. Post-layout reliability verification is an effective solution to this challenge. However, the implementation of a full-chip verification on signal electromigration requires a huge number of interconnect current calculations. The dynamic current calculation methods established on time domain circuit simulators are prohibitively expensive of runtime when applied to DSM (deep sub-micron) ICs. We propose an efficient static current calculation technique. A notable characteristic of this technique is that current calculations are based on ramp input signals, a more realistic signal than a step input. Moreover, an advanced gate model is applied to this technique; thus the current it yields is more accurate than that using a switch-resistor model. Since different electromigration models require different types of interconnect current values in their evaluation, this technique can handle the calculation of average, RMS and peak currents in order to perform a comprehensive reliability validation in IC designs. The experimental results demonstrate the efficiency and accuracy of this technique. Combined with a pruning technique, it is integrated into a reliability verification flow to be tested on a SoC design.