TY - GEN
T1 - Cross-layer resilience in low-voltage digital systems
T2 - 35th IEEE International Conference on Computer Design, ICCD 2017
AU - Cheng, Eric
AU - Abraham, Jacob
AU - Bose, Pradip
AU - Buyuktosunoglu, Alper
AU - Campbell, Keith
AU - Chen, Deming
AU - Cher, Cheng Yong
AU - Cho, Hyungmin
AU - Le, Binh
AU - Lilja, Klas
AU - Mirkhani, Shahrzad
AU - Skadron, Kevin
AU - Stan, Mircea
AU - Szafaryn, Lukasz
AU - Vezyrtzis, Christos
AU - Mitra, Subhasish
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/11/22
Y1 - 2017/11/22
N2 - CLEAR (Cross-Layer Exploration for Architecting Resilience) is a first of its kind framework which overcomes a major challenge in the design of digital systems that are resilient to hardware errors: achieve desired resilience targets at low cost (energy, power, execution time, area) by combining resilience techniques across various layers of the system stack (circuit, logic, architecture, software, algorithm). CLEAR automatically and systematically explores the large space of resilience techniques and their combinations, derives cost-effective solutions, provides guidelines for designing new techniques, and offers insights into how to design cost-effective digital systems resilient to hardware errors: 1. circuit-level techniques are crucial; 2. application-level guidance is essential; 3. existing architecture and software techniques are generally expensive or provide too little resilience; 4. some previously published techniques suffer from inaccurate analysis, leading to incorrect conclusions; 5. cost-effective protection from multiple error sources is achieved by combining techniques targeting each specific error source.
AB - CLEAR (Cross-Layer Exploration for Architecting Resilience) is a first of its kind framework which overcomes a major challenge in the design of digital systems that are resilient to hardware errors: achieve desired resilience targets at low cost (energy, power, execution time, area) by combining resilience techniques across various layers of the system stack (circuit, logic, architecture, software, algorithm). CLEAR automatically and systematically explores the large space of resilience techniques and their combinations, derives cost-effective solutions, provides guidelines for designing new techniques, and offers insights into how to design cost-effective digital systems resilient to hardware errors: 1. circuit-level techniques are crucial; 2. application-level guidance is essential; 3. existing architecture and software techniques are generally expensive or provide too little resilience; 4. some previously published techniques suffer from inaccurate analysis, leading to incorrect conclusions; 5. cost-effective protection from multiple error sources is achieved by combining techniques targeting each specific error source.
KW - Cross-layer resilience
KW - Soft errors
KW - Voltage noise
UR - http://www.scopus.com/inward/record.url?scp=85041651215&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85041651215&partnerID=8YFLogxK
U2 - 10.1109/ICCD.2017.103
DO - 10.1109/ICCD.2017.103
M3 - Conference contribution
AN - SCOPUS:85041651215
T3 - Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017
SP - 593
EP - 596
BT - Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 5 November 2017 through 8 November 2017
ER -