@inproceedings{054abfe8de6143cf8b887b600ca1ba2d,
title = "CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems",
abstract = "Circuit partitioning is a critical step in hardware-assisted functional verification that involves splitting a circuit into multiple partitions and assigning them to specific hardware. However, partitioning a large circuit can require considerable computation resources and time, especially when complex hardware constraints are involved. Moreover, the path delay after partitioning can have a significant impact on verification efficiency, making early path delay prediction crucial for refining the circuit effectively. In this work, we propose a novel circuit partitioning predictor, named CPP, to rapidly and accurately predict the path delay after partitioning. To achieve this, we use circuit coarsening to develop a multi-level path representation and employ a convolutional neural network (CNN) that can capture both local and global path structures for delay prediction. Through extensive experiments on large industrial circuits, we demonstrate the superiority of our prediction framework.",
keywords = "circuit verification, partitioning, synthesis",
author = "Xinshi Zang and Lei Chen and Xing Li and Thong, \{Wilson W.K.\} and Weihua Sheng and Young, \{Evangeline F.Y.\} and Wong, \{Martin D.F.\}",
note = "Publisher Copyright: {\textcopyright} 2023 ACM.; 33rd Great Lakes Symposium on VLSI, GLSVLSI 2023 ; Conference date: 05-06-2023 Through 07-06-2023",
year = "2023",
month = jun,
day = "5",
doi = "10.1145/3583781.3590289",
language = "English (US)",
series = "Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI",
publisher = "Association for Computing Machinery",
pages = "357--361",
booktitle = "GLSVLSI 2023 - Proceedings of the Great Lakes Symposium on VLSI 2023",
address = "United States",
}