TY - GEN
T1 - CPP
T2 - 33rd Great Lakes Symposium on VLSI, GLSVLSI 2023
AU - Zang, Xinshi
AU - Chen, Lei
AU - Li, Xing
AU - Thong, Wilson W.K.
AU - Sheng, Weihua
AU - Young, Evangeline F.Y.
AU - Wong, Martin D.F.
N1 - Publisher Copyright:
© 2023 ACM.
PY - 2023/6/5
Y1 - 2023/6/5
N2 - Circuit partitioning is a critical step in hardware-assisted functional verification that involves splitting a circuit into multiple partitions and assigning them to specific hardware. However, partitioning a large circuit can require considerable computation resources and time, especially when complex hardware constraints are involved. Moreover, the path delay after partitioning can have a significant impact on verification efficiency, making early path delay prediction crucial for refining the circuit effectively. In this work, we propose a novel circuit partitioning predictor, named CPP, to rapidly and accurately predict the path delay after partitioning. To achieve this, we use circuit coarsening to develop a multi-level path representation and employ a convolutional neural network (CNN) that can capture both local and global path structures for delay prediction. Through extensive experiments on large industrial circuits, we demonstrate the superiority of our prediction framework.
AB - Circuit partitioning is a critical step in hardware-assisted functional verification that involves splitting a circuit into multiple partitions and assigning them to specific hardware. However, partitioning a large circuit can require considerable computation resources and time, especially when complex hardware constraints are involved. Moreover, the path delay after partitioning can have a significant impact on verification efficiency, making early path delay prediction crucial for refining the circuit effectively. In this work, we propose a novel circuit partitioning predictor, named CPP, to rapidly and accurately predict the path delay after partitioning. To achieve this, we use circuit coarsening to develop a multi-level path representation and employ a convolutional neural network (CNN) that can capture both local and global path structures for delay prediction. Through extensive experiments on large industrial circuits, we demonstrate the superiority of our prediction framework.
KW - circuit verification
KW - partitioning
KW - synthesis
UR - http://www.scopus.com/inward/record.url?scp=85163214052&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85163214052&partnerID=8YFLogxK
U2 - 10.1145/3583781.3590289
DO - 10.1145/3583781.3590289
M3 - Conference contribution
AN - SCOPUS:85163214052
T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
SP - 357
EP - 361
BT - GLSVLSI 2023 - Proceedings of the Great Lakes Symposium on VLSI 2023
PB - Association for Computing Machinery
Y2 - 5 June 2023 through 7 June 2023
ER -