CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems

Xinshi Zang, Lei Chen, Xing Li, Wilson W.K. Thong, Weihua Sheng, Evangeline F.Y. Young, Martin D.F. Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Circuit partitioning is a critical step in hardware-assisted functional verification that involves splitting a circuit into multiple partitions and assigning them to specific hardware. However, partitioning a large circuit can require considerable computation resources and time, especially when complex hardware constraints are involved. Moreover, the path delay after partitioning can have a significant impact on verification efficiency, making early path delay prediction crucial for refining the circuit effectively. In this work, we propose a novel circuit partitioning predictor, named CPP, to rapidly and accurately predict the path delay after partitioning. To achieve this, we use circuit coarsening to develop a multi-level path representation and employ a convolutional neural network (CNN) that can capture both local and global path structures for delay prediction. Through extensive experiments on large industrial circuits, we demonstrate the superiority of our prediction framework.

Original languageEnglish (US)
Title of host publicationGLSVLSI 2023 - Proceedings of the Great Lakes Symposium on VLSI 2023
PublisherAssociation for Computing Machinery
Number of pages5
ISBN (Electronic)9798400701252
StatePublished - Jun 5 2023
Externally publishedYes
Event33rd Great Lakes Symposium on VLSI, GLSVLSI 2023 - Knoxville, United States
Duration: Jun 5 2023Jun 7 2023

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI


Conference33rd Great Lakes Symposium on VLSI, GLSVLSI 2023
Country/TerritoryUnited States


  • circuit verification
  • partitioning
  • synthesis

ASJC Scopus subject areas

  • General Engineering


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