Correction prediction: Reducing error correction latency for on-chip memories

Henry Duwe, Xun Jian, Rakesh Kumar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The reliability of on-chip memories (e.g., caches) determines their minimum operating voltage (Vmin) and, therefore, the power these memories consume. A strong error correction mechanism can be used to tolerate the increasing memory cell failure rate as supply voltage is reduced. However, strong error correction often incurs a high latency relative to the on-chip memory access time. We propose correction prediction where a fast mechanism predicts the result of strong error correction to hide the long latency of correction. Subsequent pipeline stages execute using the predicted values while the long latency strong error correction attempts to verify the correctness of the predicted values in parallel. We present a simple correction prediction implementation, CP, which uses a fast, but weak error correction mechanism as the correction predictor. Our evaluations for a 32KB 4-way set associative SRAM LI cache show that the proposed implementation, CP, reduces the average cache access latency by 38%-52% compared to using a strong error correction scheme alone. This reduces the energy of a 2-issue in-order core by 16%-21%.

Original languageEnglish (US)
Title of host publication2015 IEEE 21st International Symposium on High Performance Computer Architecture, HPCA 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages463-475
Number of pages13
ISBN (Electronic)9781479989300
DOIs
StatePublished - Mar 6 2015
Event2015 21st IEEE International Symposium on High Performance Computer Architecture, HPCA 2015 - Burlingame, United States
Duration: Feb 7 2015Feb 11 2015

Publication series

Name2015 IEEE 21st International Symposium on High Performance Computer Architecture, HPCA 2015

Other

Other2015 21st IEEE International Symposium on High Performance Computer Architecture, HPCA 2015
CountryUnited States
CityBurlingame
Period2/7/152/11/15

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ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Software

Cite this

Duwe, H., Jian, X., & Kumar, R. (2015). Correction prediction: Reducing error correction latency for on-chip memories. In 2015 IEEE 21st International Symposium on High Performance Computer Architecture, HPCA 2015 (pp. 463-475). [7056055] (2015 IEEE 21st International Symposium on High Performance Computer Architecture, HPCA 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/HPCA.2015.7056055