Core architecture optimization for heterogeneous chip multiprocessors

Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to design such a processor; instead, they started with an assumed combination of pre-existing cores. This work assumes the flexibility to design a multi-core architecture from the ground up and seeks to address the following question: what should be the characteristics of the cores for a heterogeneous multi-processor for the highest area or power efficiency? The study is done for varying degrees of thread-level parallelism and for different area and power budgets. The most efficient chip multiprocessors are shown to be heterogeneous, with each core customized to a different subset of application characteristics - no single core is necessarily well suited to all applications. The performance ordering of cores on such processors is different for different applications; there is only a partial ordering among cores in terms of resources and complexity. This methodology produces performance gains as high as 40%. The performance improvements come with the added cost of customization.

Original languageEnglish (US)
Title of host publicationPACT 2006 - Proceedings of the Fifteenth International Conference on Parallel Architectures and Compilation Techniques
Pages23-32
Number of pages10
DOIs
StatePublished - 2006
Externally publishedYes
EventPACT 2006 - 15th International Conference on Parallel Architectures and Compilation Techniques - Seattle, WA, United States
Duration: Sep 16 2006Sep 20 2006

Publication series

NameParallel Architectures and Compilation Techniques - Conference Proceedings, PACT
Volume2006
ISSN (Print)1089-795X

Other

OtherPACT 2006 - 15th International Conference on Parallel Architectures and Compilation Techniques
CountryUnited States
CitySeattle, WA
Period9/16/069/20/06

Keywords

  • Computer architecture
  • Heterogeneous chip multiprocessors
  • Multi-core architectures

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture

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