@inproceedings{b8bfce5ad00d45279a6f71c9b0e8e84d,
title = "CoPlace: Coherent Placement Engine with Layout-aware Partitioning for 3D ICs",
abstract = "The emerging technologies of 3D integrated circuits (3DICs) unveil a new avenue for expanding the design space into the 3D domain and present the opportunity to overcome the bottleneck of Moore's Law for the traditional 2DICs. Among various technologies, the face-to-face bonding structure provides high integration density and reliable performance. Most commercial EDA tools, however, do not support 3DIC and cannot give a convincing solution. To exploit the benefits of stacking multiple tiers vertically, placement algorithms for 3DIC are imperatively in need. In this paper, we proposed a design flow that optimizes partitioning and placement quality for 3DICs in a unified way. Experimental results on the ICCAD2022 contest benchmark show that our work outperforms the first-place team by 3.35% in quality with less runtime and terminals used.",
keywords = "3D IC, Global placement, Partitioning, Physical design",
author = "Bangqi Fu and Lixin Liu and Yang Sun and Lau, {Wing Ho} and Wong, {Martin D.F.} and Young, {Evangeline F.Y.}",
note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 29th Asia and South Pacific Design Automation Conference, ASP-DAC 2024 ; Conference date: 22-01-2024 Through 25-01-2024",
year = "2024",
doi = "10.1109/ASP-DAC58780.2024.10473808",
language = "English (US)",
series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "65--70",
booktitle = "ASP-DAC 2024 - 29th Asia and South Pacific Design Automation Conference, Proceedings",
address = "United States",
}