TY - GEN
T1 - Control flow optimization for supercomputer scalar processing
AU - Chang, Pohua P.
AU - Hwu, Wen Mei W.
N1 - Funding Information:
Acknowledgements This research has been supported by the National Science Fundation (NSF) under Grant MIP-8809478, a donation from NCR, the National Aeronautics and Space Administration (NASA) under Contract NASA NAG 1-613 in cooperation with the Illinois Computer laboratory for Aerospace Systems and Software (ICLASS), the Office of Naval Research under Contract NOO014-88-K-0656, and the University of Illinois Campus Research Board.
Publisher Copyright:
© 1989 ACM.
PY - 1989/6/1
Y1 - 1989/6/1
N2 - Control intensive scalar programs pose a very different challenge to highly pipelined supercomputers than vectorizable numeric applications. Function call/return and branch instructions disrupt the flow of instructions through the pipeline, degrading the utilization of the pipelined datapaths. This paper describes control flow optimization for scalar processing using an optimizing compiler. To obtain program control flow information, a system independent profiler has been integrated into the IMPACT-IC compiler. The control flow information obtained is converted into a weighted control graph. Based on the weighted control graph, function inline expansion, multi-way branch layout, and software branch prediction can be implemented. Using better compiler technology results in a very low cost hardware control unit (architecture) for high performance scalar processors.
AB - Control intensive scalar programs pose a very different challenge to highly pipelined supercomputers than vectorizable numeric applications. Function call/return and branch instructions disrupt the flow of instructions through the pipeline, degrading the utilization of the pipelined datapaths. This paper describes control flow optimization for scalar processing using an optimizing compiler. To obtain program control flow information, a system independent profiler has been integrated into the IMPACT-IC compiler. The control flow information obtained is converted into a weighted control graph. Based on the weighted control graph, function inline expansion, multi-way branch layout, and software branch prediction can be implemented. Using better compiler technology results in a very low cost hardware control unit (architecture) for high performance scalar processors.
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U2 - 10.1145/318789.318806
DO - 10.1145/318789.318806
M3 - Conference contribution
AN - SCOPUS:12744274257
T3 - Proceedings of the International Conference on Supercomputing
SP - 145
EP - 153
BT - Proceedings of the 3rd International Conference on Supercomputing, ICS 1989
PB - Association for Computing Machinery
T2 - 3rd International Conference on Supercomputing, ICS 1989
Y2 - 5 June 1989 through 9 June 1989
ER -