Continuous-time optimization of gate timing for synchronous rectification

Jonathan Kimball, Philip T. Krein

Research output: Contribution to conferencePaperpeer-review

Abstract

Synchronous rectifiers, which use a controlled MOSFET in place of a standard p-n or Schottky rectifier, are an important technology for low-voltage power converters. Conventional control techniques for synchronous rectification are often very conservative, however, leaving room for improvement. This paper presents a method for monitoring current flow to adaptively optimize the relative timing of two gate signals for a buck converter with synchronous rectification. Theoretical development is given, along with experimental results for two low-voltage converters.

Original languageEnglish (US)
Pages1015-1018
Number of pages4
StatePublished - 1996
Externally publishedYes
EventProceedings of the 1996 IEEE 39th Midwest Symposium on Circuits & Systems. Part 3 (of 3) - Ames, IA, USA
Duration: Aug 18 1996Aug 21 1996

Other

OtherProceedings of the 1996 IEEE 39th Midwest Symposium on Circuits & Systems. Part 3 (of 3)
CityAmes, IA, USA
Period8/18/968/21/96

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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