Continuous-time input pipeline ADCs

David Gubbins, Bumha Lee, Pavan Kumar Hanumolu, Un Ku Moon

Research output: Contribution to journalArticlepeer-review


Two continuous-time input pipeline ADC architectures are introduced. The continuous-time input approach overcomes many of the challenges associated with a pure switched-capacitor architecture. The resistive input load of the two new architectures provides a benign interface to external drive circuitry. The switched-capacitor sampling function is moved to the second stage input which greatly eases the sampling distortion requirements and obviates the need for an explicit front-end sample-and-hold function. The second ADC presented additionally provides inherent anti-alias filtering, allowing the possibility of eliminating costly anti-alias filters. This second architecture also eases the jitter requirements of the ADC clock when compared to switched capacitor pipeline ADCs. Measured results obtained from two proof of concept test chips fabricated in a 0.18 μm CMOS process validate the effectiveness of the proposed techniques.

Original languageEnglish (US)
Article number5518502
Pages (from-to)1456-1468
Number of pages13
JournalIEEE Journal of Solid-State Circuits
Issue number8
StatePublished - Aug 2010
Externally publishedYes


  • Analog-to-digital conversion
  • CMOS analog integrated circuits
  • anti-alias filter
  • continuous time
  • pipeline

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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