Continuous optimization

Brian Fahs, Todd Rafacz, Sanjay J. Patel, Steven S. Lumetta

Research output: Contribution to journalConference articlepeer-review


This paper presents a hardware-based dynamic optimizer that continuously optimizes an application's instruction stream. In continuous optimization, dataflow optimizations are performed using simple, table-based hardware placed in the rename stage of the processor pipeline. The continuous optimizer reduces dataflow height by performing constant propagation, reassociation, redundant load elimination, store forwarding, and silent store removal. To enhance the impact of the optimizations, the optimizer integrates values generated by the execution units back into the optimization process. Continuous optimization allows instructions with input values known at optimization time to be executed in the optimizer, leaving less work for the out-of-order portion of the pipeline. Continuous optimization can detect branch mispredictions earlier and thus reduce the misprediction penalty. In this paper, we present a detailed description of a hardware optimizer and evaluate it in the context of a contemporary microarchitecture running current workloads. Our analysis of SPECint, SPECfp, and mediabench workloads reveals that a hardware optimizer can directly execute 33% of instructions, resolve 29% of mispredicted branches, and generate addresses for 76% of memory operations. These positive effects combine to provide speed ups in the range 0.99 to 1.27.

Original languageEnglish (US)
Pages (from-to)86-97
Number of pages12
JournalProceedings - International Symposium on Computer Architecture
StatePublished - 2005
Event32nd Interntional Symposium on Computer Architecture, ISCA 2005 - Madison, WI, United States
Duration: Jun 4 2005Jun 8 2005

ASJC Scopus subject areas

  • General Engineering


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