Conjoined-core chip multiprocessing

Rakesh Kumar, Norman P. Jouppi, Dean M. Tullsen

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Chip Multiprocessors (CMP) and Simultaneous Multithreading (SMT) are two approaches that have been proposed to increase processor efficiency. We believe these two approaches are two extremes of a viable spectrum. Between these two extremes, there exists a range of possible architectures, sharing varying degrees of hardware between processors or threads. This paper proposes conjoined-core chip multiprocessing - topologically feasible resource sharing between adjacent cores of a chip multiprocessor to reduce die area with minimal impact on performance and hence improving the overall computational efficiency. It investigates the possible sharing of floating-point units, crossbar ports, instruction caches, and data caches and details the area savings that each kind of sharing entails. It also shows that the negative impact on performance due to sharing is significantly less than the benefits of reduced area. Several novel techniques for intelligent sharing of the hardware resources to minimize performance degradation are presented.

Original languageEnglish (US)
Title of host publicationProceedings of the 37th Annual International Symposium on Microarchitecture, MICRO-37 2004
Number of pages12
StatePublished - 2004
Externally publishedYes
Event37th International Symposium on Microarchitecture - MICRO-37 2004 - Portland, OR, United States
Duration: Dec 4 2004Dec 8 2004

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
ISSN (Print)1072-4451


Other37th International Symposium on Microarchitecture - MICRO-37 2004
Country/TerritoryUnited States
CityPortland, OR

ASJC Scopus subject areas

  • General Engineering


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