Abstract
Traditional integrated circuit design achieves error-free operation by designing with margins (clock frequency and supply voltage) and/or including hardware replication and recomputation, which may counter the full energy and area benefits of aggressive technology scaling. It is thus desirable that modern systems-on-chip (SoCs) permit hardware errors while maintaining robust system-level performance. Treating hardware errors as computational noise and extending traditional estimation theory to include practical SoC design constraints yields a novel and general design optimization framework. This work demonstrates the breadth of applicability of the estimation-theoretic framework for system design by showcasing two different application classes that demonstrate 36% to 50% power reduction.
Original language | English (US) |
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Article number | 5458004 |
Pages (from-to) | 4416-4421 |
Number of pages | 6 |
Journal | IEEE Transactions on Signal Processing |
Volume | 58 |
Issue number | 8 |
DOIs | |
State | Published - Aug 2010 |
Keywords
- Applications of statistical signal processing techniques
- HDW-LPWR
- low-power signal processing techniques and architectures
ASJC Scopus subject areas
- Signal Processing
- Electrical and Electronic Engineering