Traditional integrated circuit design achieves error-free operation by designing with margins (clock frequency and supply voltage) and/or including hardware replication and recomputation, which may counter the full energy and area benefits of aggressive technology scaling. It is thus desirable that modern systems-on-chip (SoCs) permit hardware errors while maintaining robust system-level performance. Treating hardware errors as computational noise and extending traditional estimation theory to include practical SoC design constraints yields a novel and general design optimization framework. This work demonstrates the breadth of applicability of the estimation-theoretic framework for system design by showcasing two different application classes that demonstrate 36% to 50% power reduction.
- Applications of statistical signal processing techniques
- low-power signal processing techniques and architectures
ASJC Scopus subject areas
- Signal Processing
- Electrical and Electronic Engineering