Computation as estimation: A general framework for robustness and energy efficiency in socs

Sriram Narayanan, Girish Vishnu Varatkar, Douglas L. Jones, Naresh R. Shanbhag

Research output: Contribution to journalArticlepeer-review


Traditional integrated circuit design achieves error-free operation by designing with margins (clock frequency and supply voltage) and/or including hardware replication and recomputation, which may counter the full energy and area benefits of aggressive technology scaling. It is thus desirable that modern systems-on-chip (SoCs) permit hardware errors while maintaining robust system-level performance. Treating hardware errors as computational noise and extending traditional estimation theory to include practical SoC design constraints yields a novel and general design optimization framework. This work demonstrates the breadth of applicability of the estimation-theoretic framework for system design by showcasing two different application classes that demonstrate 36% to 50% power reduction.

Original languageEnglish (US)
Article number5458004
Pages (from-to)4416-4421
Number of pages6
JournalIEEE Transactions on Signal Processing
Issue number8
StatePublished - Aug 2010


  • Applications of statistical signal processing techniques
  • low-power signal processing techniques and architectures

ASJC Scopus subject areas

  • Signal Processing
  • Electrical and Electronic Engineering


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