A comprehensive modeling methodology is presented for the investigation of on-chip noise generation and coupling due to power switching. The methodology utilizes a comprehensive electromagnetic model for the on-chip portion of the power grid. Thus, the tedious and error-prone extraction of a distributed RLC model for the power grid is avoided and the generated model allows for power grid induced broadband and distributed noise coupling to be taken into account in the transient simulation. The electromagnetic model for the power grid is complemented by a distributed RC model for the semiconductor substrate and RLCG models for the interconnects. Thus, a comprehensive model results for the quantification of on-chip interconnect and power grid noise effects during switching. Transient simulations using this model are carried out using a hybrid time-domain integration scheme which combines a SPICE-like engine for the analysis of all RLCG netlists and the nonlinear drivers incorporated in the model with a numerical integration algorithm for the discrete electromagnetic model for the power grid.