TY - GEN
T1 - Comprehending In-memory Computing Trends via Proper Benchmarking
AU - Shanbhag, Naresh R.
AU - Roy, Saion K.
N1 - This work was supported by DARPA via the ERI FRANC program, and by the Semiconductor Research Corporation (SRC) via the Center on Brain-Inspired Computing (C-BRIC).
PY - 2022
Y1 - 2022
N2 - Since its inception in 2014 [1], the modern version of in-memory computing (IMC) has become an active area of research in integrated circuit design globally for realizing artificial intelligence and machine learning workloads. Since 2018, > 40 IMC-related papers have been published in top circuit design conferences demonstrating significant reductions (>20X) in energy over their digital counterparts especially at the bank-level. Today, bank-level IMC designs have matured but it is not clear what the limiting factors are. This lack of clarity is due to multiple reasons including: 1) the conceptual complexity of IMCs due to its full-stack (devices-to-systems) nature, 2) the presence of a fundamental energy-efficiency vs. compute SNR trade-off due to its analog computations, and 3) the statistical nature of machine learning workloads. The absence of a rigorous benchmarking methodology for IMCs - a problem facing machine learning ICs in general [2] - further obfuscates the underlying trade-offs. As a result, it has become difficult to evaluate the novelty of IMC-related ideas being proposed and therefore gauge the true progress in this exciting field.
AB - Since its inception in 2014 [1], the modern version of in-memory computing (IMC) has become an active area of research in integrated circuit design globally for realizing artificial intelligence and machine learning workloads. Since 2018, > 40 IMC-related papers have been published in top circuit design conferences demonstrating significant reductions (>20X) in energy over their digital counterparts especially at the bank-level. Today, bank-level IMC designs have matured but it is not clear what the limiting factors are. This lack of clarity is due to multiple reasons including: 1) the conceptual complexity of IMCs due to its full-stack (devices-to-systems) nature, 2) the presence of a fundamental energy-efficiency vs. compute SNR trade-off due to its analog computations, and 3) the statistical nature of machine learning workloads. The absence of a rigorous benchmarking methodology for IMCs - a problem facing machine learning ICs in general [2] - further obfuscates the underlying trade-offs. As a result, it has become difficult to evaluate the novelty of IMC-related ideas being proposed and therefore gauge the true progress in this exciting field.
UR - http://www.scopus.com/inward/record.url?scp=85130699907&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85130699907&partnerID=8YFLogxK
U2 - 10.1109/CICC53496.2022.9772817
DO - 10.1109/CICC53496.2022.9772817
M3 - Conference contribution
AN - SCOPUS:85130699907
T3 - Proceedings of the Custom Integrated Circuits Conference
BT - 2022 IEEE Custom Integrated Circuits Conference, CICC 2022 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 43rd Annual IEEE Custom Integrated Circuits Conference, CICC 2022
Y2 - 24 April 2022 through 27 April 2022
ER -