@inproceedings{2774537bb1fe488e9ca69f3fa98d9161,
title = "Compiling for instruction cache performance on a multithreaded architecture",
abstract = "Instruction cache aware compilation seeks to lay out a program in memory in such a way that cache conflicts between procedures are minimized. It does this through profile-driven knowledge of procedure invocation patterns. On a multithreaded architecture, however, more conflicts may arise between threads than between procedures on the same thread. This research examines opportunities for the compiler to optimize instruction cache layout on a multithreaded architecture. We examine scenarios where (1) the compiler has knowledge about multiple programs that will be or are likely to be co-scheduled, and where (2) the compiler has no knowledge at compile time of which applications will be co-scheduled. We present solutions for both environments.",
keywords = "Communication system control, Computer architecture, Computer science, Hardware, Multithreading, Operating systems, Optimizing compilers, Program processors, Surface-mount technology, Yarn",
author = "Rakesh Kumar and Tullsen, {Dean M.}",
note = "Publisher Copyright: {\textcopyright} 2002 IEEE.; 35th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2002 ; Conference date: 18-11-2002 Through 22-11-2002",
year = "2002",
doi = "10.1109/MICRO.2002.1176269",
language = "English (US)",
series = "Proceedings of the Annual International Symposium on Microarchitecture, MICRO",
publisher = "IEEE Computer Society",
pages = "419--429",
booktitle = "Proceedings - 35th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2002",
}