Compiler techniques for high performance sequentially consistent java programs

Zehra Sura; Xing Fang; Chi Leung Wong; Samuel P. Midkiff; Jaejin Lee; David Padua

doi:10.1145/1065944.1065947

Compiler techniques for high performance sequentially consistent java programs

Zehra Sura, Xing Fang, Chi Leung Wong, Samuel P. Midkiff, Jaejin Lee, David Padua

Siebel School of Computing and Data Science

Research output: Contribution to conference › Paper › peer-review

Abstract

The rise of Java, C#, and other explicitly parallel languages has increased the importance of compiling for different software memory models. This paper describes co-operating escape, thread structure, and delay set analyses that enable high performance for sequentially consistent programs. We compare the performance of a set of Java programs compiled for sequential consistency (SC) with the performance of the same programs compiled for weak consistency. For SC, we observe a slowdown of 10% on average for an architecture based on the Intel Xeon processor, and 26% on average for an architecture based on the IBM Power3.

Original language	English (US)
Pages	2-13
Number of pages	12
DOIs	https://doi.org/10.1145/1065944.1065947
State	Published - 2005
Event	2005 ACM SIGPLAN Symposium on Principles and Practise of Parallel Programming, PROPP 05 - Chicago, IL, United States Duration: Jun 15 2005 → Jun 17 2005

Conference

Conference	2005 ACM SIGPLAN Symposium on Principles and Practise of Parallel Programming, PROPP 05
Country/Territory	United States
City	Chicago, IL
Period	6/15/05 → 6/17/05

Keywords

Java
Memory consistency
Multithread
Synchronization

ASJC Scopus subject areas

Software

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10.1145/1065944.1065947

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title = "Compiler techniques for high performance sequentially consistent java programs",

abstract = "The rise of Java, C#, and other explicitly parallel languages has increased the importance of compiling for different software memory models. This paper describes co-operating escape, thread structure, and delay set analyses that enable high performance for sequentially consistent programs. We compare the performance of a set of Java programs compiled for sequential consistency (SC) with the performance of the same programs compiled for weak consistency. For SC, we observe a slowdown of 10% on average for an architecture based on the Intel Xeon processor, and 26% on average for an architecture based on the IBM Power3.",

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author = "Zehra Sura and Xing Fang and Wong, {Chi Leung} and Midkiff, {Samuel P.} and Jaejin Lee and David Padua",

year = "2005",

doi = "10.1145/1065944.1065947",

language = "English (US)",

pages = "2--13",

note = "2005 ACM SIGPLAN Symposium on Principles and Practise of Parallel Programming, PROPP 05 ; Conference date: 15-06-2005 Through 17-06-2005",

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T1 - Compiler techniques for high performance sequentially consistent java programs

AU - Sura, Zehra

AU - Fang, Xing

AU - Wong, Chi Leung

AU - Midkiff, Samuel P.

AU - Lee, Jaejin

AU - Padua, David

PY - 2005

Y1 - 2005

N2 - The rise of Java, C#, and other explicitly parallel languages has increased the importance of compiling for different software memory models. This paper describes co-operating escape, thread structure, and delay set analyses that enable high performance for sequentially consistent programs. We compare the performance of a set of Java programs compiled for sequential consistency (SC) with the performance of the same programs compiled for weak consistency. For SC, we observe a slowdown of 10% on average for an architecture based on the Intel Xeon processor, and 26% on average for an architecture based on the IBM Power3.

AB - The rise of Java, C#, and other explicitly parallel languages has increased the importance of compiling for different software memory models. This paper describes co-operating escape, thread structure, and delay set analyses that enable high performance for sequentially consistent programs. We compare the performance of a set of Java programs compiled for sequential consistency (SC) with the performance of the same programs compiled for weak consistency. For SC, we observe a slowdown of 10% on average for an architecture based on the Intel Xeon processor, and 26% on average for an architecture based on the IBM Power3.

KW - Java

KW - Memory consistency

KW - Multithread

KW - Synchronization

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T2 - 2005 ACM SIGPLAN Symposium on Principles and Practise of Parallel Programming, PROPP 05

Y2 - 15 June 2005 through 17 June 2005

ER -

Compiler techniques for high performance sequentially consistent java programs

Abstract

Conference

Keywords

ASJC Scopus subject areas

Online availability

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