Compiler techniques for high performance sequentially consistent java programs

Zehra Sura, Xing Fang, Chi Leung Wong, Samuel P. Midkiff, Jaejin Lee, David A Padua

Research output: Contribution to conferencePaper

Abstract

The rise of Java, C#, and other explicitly parallel languages has increased the importance of compiling for different software memory models. This paper describes co-operating escape, thread structure, and delay set analyses that enable high performance for sequentially consistent programs. We compare the performance of a set of Java programs compiled for sequential consistency (SC) with the performance of the same programs compiled for weak consistency. For SC, we observe a slowdown of 10% on average for an architecture based on the Intel Xeon processor, and 26% on average for an architecture based on the IBM Power3.

Original languageEnglish (US)
Pages2-13
Number of pages12
DOIs
StatePublished - Dec 1 2005
Event2005 ACM SIGPLAN Symposium on Principles and Practise of Parallel Programming, PROPP 05 - Chicago, IL, United States
Duration: Jun 15 2005Jun 17 2005

Other

Other2005 ACM SIGPLAN Symposium on Principles and Practise of Parallel Programming, PROPP 05
CountryUnited States
CityChicago, IL
Period6/15/056/17/05

Keywords

  • Java
  • Memory consistency
  • Multithread
  • Synchronization

ASJC Scopus subject areas

  • Software

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  • Cite this

    Sura, Z., Fang, X., Wong, C. L., Midkiff, S. P., Lee, J., & Padua, D. A. (2005). Compiler techniques for high performance sequentially consistent java programs. 2-13. Paper presented at 2005 ACM SIGPLAN Symposium on Principles and Practise of Parallel Programming, PROPP 05, Chicago, IL, United States. https://doi.org/10.1145/1065944.1065947