Compiler Support for Software Cache Coherence

Sanket Tavarageri, Wooil Kim, Josep Torrellas, P. Sadayappan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The advent of multi-core processors with a largenumber of cores and heterogeneous architecture poses challengesfor achieving scalable cache coherence. Several recent researchefforts have focused on simplifying or abandoning hardwarecache coherence protocols. However, this adds a significantburden on the programmer, unless automated compiler supportis developed. In this paper, we develop compiler support for parallel systemsthat delegate the task of maintaining cache coherence to software. Algorithms to automatically insert software cache coherence instructions into parallel applications are presented. This freesthe programmer from having to manually insert coherenceannotations, which can be tedious and error-prone. Experimental evaluation over a number of benchmarks demonstrates thateffective compiler techniques can make software cache coherencecompetitive with hardware coherence schemes both in terms ofenergy and performance.

Original languageEnglish (US)
Title of host publicationProceedings - 23rd IEEE International Conference on High Performance Computing, HiPC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages341-350
Number of pages10
ISBN (Electronic)9781509054114
DOIs
StatePublished - Feb 1 2017
Event23rd IEEE International Conference on High Performance Computing, HiPC 2016 - Hyderabad, India
Duration: Dec 19 2016Dec 22 2016

Publication series

NameProceedings - 23rd IEEE International Conference on High Performance Computing, HiPC 2016

Other

Other23rd IEEE International Conference on High Performance Computing, HiPC 2016
CountryIndia
CityHyderabad
Period12/19/1612/22/16

Keywords

  • Compiler Support
  • Software Cache Coherence

ASJC Scopus subject areas

  • Hardware and Architecture

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