Compiler code transformations for superscalar-based high-performance systems

Scott A. Mahlke, William Y. Chen, John C. Gyuenhaal, Wen Mei W. Hwu, Pohua P. Chang, Tokuzo Kiyohara

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Exploiting parallelism at both the multiprocessor level and the instruction level is an effective means for supercomputers to achieve high-performance. The amount of instruction-level parallelism available to superscalar or VLIW node processors can be limited, however, with conventional compiler optimization techniques. In this paper, a set of compiler transformations designed to increase instruction-level parallelism is described. The effectiveness of these transformations is evaluated using 40 loop nests extracted from a range of supercomputer applications. This evaluation shows that increasing execution resources in superscalar/VLIW node processors yields little performance improvement unless loop unrolling and register renaming are applied. It also reveals that these two transformations are sufficient for DOALL loops. However, more advanced transformations are required in order for serial and DOACROSS loops to fully benefit from the increased execution resources. The results show that the six additional transformations studied satisfy most of this need.

Original languageEnglish (US)
Title of host publicationProceedings of the 1992 ACM/IEEE conference on Supercomputing, Supercomputing 1992
EditorsRobert Werner
PublisherAssociation for Computing Machinery
Number of pages10
ISBN (Electronic)0818626305
StatePublished - Dec 1 1992
Event1992 ACM/IEEE conference on Supercomputing, Supercomputing 1992 - Minneapolis, United States
Duration: Nov 16 1992Nov 20 1992

Publication series

NameProceedings of the International Conference on Supercomputing
VolumePart F129723


Other1992 ACM/IEEE conference on Supercomputing, Supercomputing 1992
CountryUnited States

ASJC Scopus subject areas

  • Computer Science(all)

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