Abstract
Multiple instruction rollback (MIR) is a technique that has been implemented in mainframe computers to provide rapid recovery from transient processor failures. Hardware-based MIR designs eliminate rollback data hazards by providing data redundancy implemented in hardware. Compiler-based MIR designs have also been developed which remove rollback data hazards directly with data-flow transformations. This paper describes compiler-assisted techniques to achieve multiple instruction rollback recovery. We observe that some data hazards resulting from instruction rollback can be resolved efficiently by providing an operand read buffer while others are resolved more efficiently with compiler transformations. The compiler-assisted scheme presented consists of hardware that is less complex than shadow files, history files, history buffers, or delayed write buffers, while experimental evaluation indicates performance improvement over compiler-based schemes.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 1096-1107 |
| Number of pages | 12 |
| Journal | IEEE Transactions on Computers |
| Volume | 44 |
| Issue number | 9 |
| DOIs | |
| State | Published - Sep 1995 |
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Keywords
- Fault-tolerance
- compilers
- error recovery
- instruction retry
ASJC Scopus subject areas
- Software
- Theoretical Computer Science
- Hardware and Architecture
- Computational Theory and Mathematics
Cite this
Compiler-Assisted Multiple Instruction Rollback Recovery Using a Read Buffer. / Alewine, Neal J.; Chen, Shyh Kwei; Fuchs, W. Kent; Hwu, Wen-Mei W.
In: IEEE Transactions on Computers, Vol. 44, No. 9, 09.1995, p. 1096-1107.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Compiler-Assisted Multiple Instruction Rollback Recovery Using a Read Buffer
AU - Alewine, Neal J.
AU - Chen, Shyh Kwei
AU - Fuchs, W. Kent
AU - Hwu, Wen-Mei W
PY - 1995/9
Y1 - 1995/9
N2 - Multiple instruction rollback (MIR) is a technique that has been implemented in mainframe computers to provide rapid recovery from transient processor failures. Hardware-based MIR designs eliminate rollback data hazards by providing data redundancy implemented in hardware. Compiler-based MIR designs have also been developed which remove rollback data hazards directly with data-flow transformations. This paper describes compiler-assisted techniques to achieve multiple instruction rollback recovery. We observe that some data hazards resulting from instruction rollback can be resolved efficiently by providing an operand read buffer while others are resolved more efficiently with compiler transformations. The compiler-assisted scheme presented consists of hardware that is less complex than shadow files, history files, history buffers, or delayed write buffers, while experimental evaluation indicates performance improvement over compiler-based schemes.
AB - Multiple instruction rollback (MIR) is a technique that has been implemented in mainframe computers to provide rapid recovery from transient processor failures. Hardware-based MIR designs eliminate rollback data hazards by providing data redundancy implemented in hardware. Compiler-based MIR designs have also been developed which remove rollback data hazards directly with data-flow transformations. This paper describes compiler-assisted techniques to achieve multiple instruction rollback recovery. We observe that some data hazards resulting from instruction rollback can be resolved efficiently by providing an operand read buffer while others are resolved more efficiently with compiler transformations. The compiler-assisted scheme presented consists of hardware that is less complex than shadow files, history files, history buffers, or delayed write buffers, while experimental evaluation indicates performance improvement over compiler-based schemes.
KW - Fault-tolerance
KW - compilers
KW - error recovery
KW - instruction retry
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UR - http://www.scopus.com/inward/citedby.url?scp=0007934730&partnerID=8YFLogxK
U2 - 10.1109/12.464388
DO - 10.1109/12.464388
M3 - Article
AN - SCOPUS:0007934730
VL - 44
SP - 1096
EP - 1107
JO - IEEE Transactions on Computers
JF - IEEE Transactions on Computers
SN - 0018-9340
IS - 9
ER -