Comparison of wafer-level with package-level CDM stress facilitated by real-time probing

Nathan Jack; Vrashank Shukla; Elyse Rosenbaum

doi:10.1109/TDMR.2011.2166399

Comparison of wafer-level with package-level CDM stress facilitated by real-time probing

Nathan Jack, Vrashank Shukla, Elyse Rosenbaum

Research output: Contribution to journal › Article › peer-review

Abstract

Using real-time voltage probing and circuit simulation, the stress induced by wafer-level charged-device-model (CDM) electrostatic discharge test methods is compared to that of package-level field-induced CDM testers. It is shown that, while wafer-level testers can replicate I/O failures, they may not replicate core failures because of differences in the induced current stress.

Original language	English (US)
Article number	6006519
Pages (from-to)	522-530
Number of pages	9
Journal	IEEE Transactions on Device and Materials Reliability
Volume	11
Issue number	4
DOIs	https://doi.org/10.1109/TDMR.2011.2166399
State	Published - Dec 2011

Keywords

CMOS integrated circuits (ICs)
IC testing
electrostatic discharge (ESD)
transmission line measurements

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Safety, Risk, Reliability and Quality
Electrical and Electronic Engineering

Online availability

10.1109/TDMR.2011.2166399

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abstract = "Using real-time voltage probing and circuit simulation, the stress induced by wafer-level charged-device-model (CDM) electrostatic discharge test methods is compared to that of package-level field-induced CDM testers. It is shown that, while wafer-level testers can replicate I/O failures, they may not replicate core failures because of differences in the induced current stress.",

keywords = "CMOS integrated circuits (ICs), IC testing, electrostatic discharge (ESD), transmission line measurements",

author = "Nathan Jack and Vrashank Shukla and Elyse Rosenbaum",

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N2 - Using real-time voltage probing and circuit simulation, the stress induced by wafer-level charged-device-model (CDM) electrostatic discharge test methods is compared to that of package-level field-induced CDM testers. It is shown that, while wafer-level testers can replicate I/O failures, they may not replicate core failures because of differences in the induced current stress.

AB - Using real-time voltage probing and circuit simulation, the stress induced by wafer-level charged-device-model (CDM) electrostatic discharge test methods is compared to that of package-level field-induced CDM testers. It is shown that, while wafer-level testers can replicate I/O failures, they may not replicate core failures because of differences in the induced current stress.

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KW - transmission line measurements

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Comparison of wafer-level with package-level CDM stress facilitated by real-time probing

Abstract

Keywords

ASJC Scopus subject areas

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