Comparison of wafer-level with package-level CDM stress facilitated by real-time probing

Nathan Jack, Vrashank Shukla, Elyse Rosenbaum

Research output: Contribution to journalArticle

Abstract

Using real-time voltage probing and circuit simulation, the stress induced by wafer-level charged-device-model (CDM) electrostatic discharge test methods is compared to that of package-level field-induced CDM testers. It is shown that, while wafer-level testers can replicate I/O failures, they may not replicate core failures because of differences in the induced current stress.

Original languageEnglish (US)
Article number6006519
Pages (from-to)522-530
Number of pages9
JournalIEEE Transactions on Device and Materials Reliability
Volume11
Issue number4
DOIs
StatePublished - Dec 1 2011

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Electrostatic discharge
Circuit simulation
Induced currents
Electric potential

Keywords

  • CMOS integrated circuits (ICs)
  • IC testing
  • electrostatic discharge (ESD)
  • transmission line measurements

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Safety, Risk, Reliability and Quality
  • Electrical and Electronic Engineering

Cite this

Comparison of wafer-level with package-level CDM stress facilitated by real-time probing. / Jack, Nathan; Shukla, Vrashank; Rosenbaum, Elyse.

In: IEEE Transactions on Device and Materials Reliability, Vol. 11, No. 4, 6006519, 01.12.2011, p. 522-530.

Research output: Contribution to journalArticle

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