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Comparison of FICDM and wafer-level CDM test methods
Nathan Jack,
Elyse Rosenbaum
Electrical and Computer Engineering
Coordinated Science Lab
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peer-review
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Keyphrases
Field-induced
100%
Wafer Level
100%
Charged Device Model
100%
Model Test Method
100%
Integrated Circuits
40%
On chip
20%
Stress-induced
20%
Current Pulse
20%
Capacitively Coupled
20%
Package Level
20%
Coupled Transmission Lines
20%
Functional Failure
20%
Voltage Monitor
20%
Circuit Failure
20%
Transmission Line Pulsing
20%
Engineering
Test Method
100%
Model Test
100%
Integrated Circuit
66%
Internals
33%
Generated Stress
33%
Induced Stress
33%
Induced Failure
33%
Current Pulse
33%
Electric Lines
33%
Circuit Core
33%
Medicine and Dentistry
Pulse Rate
100%