Comparison of FICDM and wafer-level CDM test methods

Nathan Jack, Elyse Rosenbaum

Research output: Contribution to journalArticle

Abstract

The on-chip stresses induced by various charged device model (CDM) test methods are compared at both the package and wafer levels. Test methods studied include field-induced CDM (FICDM), wafer-level CDM (WCDM2), capacitively coupled transmission-line pulsing (CC-TLP), and very fast TLP (VF-TLP). The generated stresses are compared on the basis of voltage monitor readings and integrated circuit (IC) functional failures. In general, core circuit failures induced by FICDM are replicated on the wafer level. Package-related parasitics can alter the externally measured FICDM current pulse relative to that delivered internal to the IC, causing miscorrelation with wafer-level testers.

Original languageEnglish (US)
Article number6515361
Pages (from-to)379-387
Number of pages9
JournalIEEE Transactions on Device and Materials Reliability
Volume13
Issue number2
DOIs
StatePublished - Jul 1 2013

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Integrated circuits
Induced currents
Electric lines
Networks (circuits)
Electric potential

Keywords

  • CMOS integrated circuits (ICs)
  • electrostatic discharge (ESD)
  • integrated circuit (IC) testing
  • transmission-line measurements

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Safety, Risk, Reliability and Quality
  • Electrical and Electronic Engineering

Cite this

Comparison of FICDM and wafer-level CDM test methods. / Jack, Nathan; Rosenbaum, Elyse.

In: IEEE Transactions on Device and Materials Reliability, Vol. 13, No. 2, 6515361, 01.07.2013, p. 379-387.

Research output: Contribution to journalArticle

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