Abstract
The on-chip stresses induced by various charged device model (CDM) test methods are compared at both the package and wafer levels. Test methods studied include field-induced CDM (FICDM), wafer-level CDM (WCDM2), capacitively coupled transmission-line pulsing (CC-TLP), and very fast TLP (VF-TLP). The generated stresses are compared on the basis of voltage monitor readings and integrated circuit (IC) functional failures. In general, core circuit failures induced by FICDM are replicated on the wafer level. Package-related parasitics can alter the externally measured FICDM current pulse relative to that delivered internal to the IC, causing miscorrelation with wafer-level testers.
| Original language | English (US) |
|---|---|
| Article number | 6515361 |
| Pages (from-to) | 379-387 |
| Number of pages | 9 |
| Journal | IEEE Transactions on Device and Materials Reliability |
| Volume | 13 |
| Issue number | 2 |
| DOIs | |
| State | Published - 2013 |
Keywords
- CMOS integrated circuits (ICs)
- electrostatic discharge (ESD)
- integrated circuit (IC) testing
- transmission-line measurements
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Safety, Risk, Reliability and Quality
- Electrical and Electronic Engineering