Scalable shared-memory multiprocessors are attractive because they achieve large-scale parallel processing without surrendering much programmability. Several such machines have been built or are currently being built, for instance RP3, Cedar, KSR1, DASH, DDM1, Alewife, Cray T3D, or the Tera computer system. While all these machines support the shared-memory paradigm, they differ significantly. For example, some of them use hardware to support cache coherence, while others rely on the compiler or the programmer to do so. Furthermore, a subset of the machines are hierarchical, and some have the processors grouped in clusters. In addition to these and other hardware issues, machines also differ in software issues. For instance, the most natural model of parallelism supported by compilers and the operating system can be task- or loop-based.
|Original language||English (US)|
|Journal||Proceedings of the International Conference on Parallel Processing|
|State||Published - Jan 1 1994|
|Event||23rd International Conference on Parallel Processing, ICPP 1994 - Raleigh, NC, United States|
Duration: Aug 15 1994 → Aug 19 1994
ASJC Scopus subject areas
- Hardware and Architecture