Comparing software and hardware schemes for reducing the cost of branches.

Wen mei W. Hwu, Thomas M. Conte, Pohua P. Chang

Research output: Contribution to journalConference articlepeer-review


Pipelining has become a common technique to increase throughput of the instruction fetch, instruction decode, and instruction execution portions of modern computers. Branch instructions disrupt the flow of instructions through the pipeline, increasing the overall execution cost of branch instructions. Three schemes to reduce the cost of branches are presented in context of a general pipeline model. Ten realistic Unix-domain programs are used to compare directly the cost and performance of the three schemes, and the results are in favor of the software-based scheme. For example, the software-based scheme has a cost of 1.65 cycles/branch, vs. a cost of 1.68 cycles/branch of the best hardware scheme for a highly pielined processor (eleven-stage pipeline). The results are 1.19 (software scheme) versus 1.23 cycles/branch (best hardware scheme) for a moderately pipelined processor (five-stage pipeline).

Original languageEnglish (US)
Pages (from-to)224-233
Number of pages10
JournalConference Proceedings - Annual Symposium on Computer Architecture
Issue number16
StatePublished - 1989
Event16th Annual International Symposium on Computer Architecture - Jerusalem, Israel
Duration: May 28 1989Jun 1 1989

ASJC Scopus subject areas

  • Engineering(all)


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