Comparative study of charge trapping effects in LDD surface-channel and buried-channel PMOS transistors using charge profiling and threshold voltage shift measurements
C. K. Kok, W. C. Chew, W. K. Chim, D. S.H. Chan, S. E. Leang
Research output: Contribution to conference › Paper › peer-review
Fingerprint
Dive into the research topics of 'Comparative study of charge trapping effects in LDD surface-channel and buried-channel PMOS transistors using charge profiling and threshold voltage shift measurements'. Together they form a unique fingerprint.