Comparative study of charge trapping effects in LDD surface-channel and buried-channel PMOS transistors using charge profiling and threshold voltage shift measurements

C. K. Kok; Weng Cho Chew; W. K. Chim; D. S.H. Chan; S. E. Leang

Comparative study of charge trapping effects in LDD surface-channel and buried-channel PMOS transistors using charge profiling and threshold voltage shift measurements

C. K. Kok, Weng Cho Chew, W. K. Chim, D. S.H. Chan, S. E. Leang

Electrical and Computer Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract

Extracted charge profiles of lightly-doped drain (LDD) surface-channel and buried-channel pMOS devices stressed under hot-carrier injection conditions reveal predominant electron trapping near the gate edge at the drain region in both cases. From threshold voltage measurements, there is some evidence of hole trapping after long stress times in surface-channel pMOSFETs, but not in buried-channel devices. Hot-electron trapping is the dominant degradation mechanism in buried-channel LDD pMOSFETs. For surface-channel LDD pMOSFETs, large concentrations of electron traps near the gate edge were found.

Original language	English (US)
Pages	200-205
Number of pages	6
State	Published - 1999
Event	Proceedings of the 1999 7th International Symposium on Physical and Failure Analysis of Integrated Circuits - Singapore, Singapore Duration: Jul 5 1999 → Jul 9 1999

Other

Other	Proceedings of the 1999 7th International Symposium on Physical and Failure Analysis of Integrated Circuits
City	Singapore, Singapore
Period	7/5/99 → 7/9/99

ASJC Scopus subject areas

Engineering(all)

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Kok, C. K., Chew, W. C., Chim, W. K., Chan, D. S. H., & Leang, S. E. (1999). Comparative study of charge trapping effects in LDD surface-channel and buried-channel PMOS transistors using charge profiling and threshold voltage shift measurements. 200-205. Paper presented at Proceedings of the 1999 7th International Symposium on Physical and Failure Analysis of Integrated Circuits, Singapore, Singapore.

Comparative study of charge trapping effects in LDD surface-channel and buried-channel PMOS transistors using charge profiling and threshold voltage shift measurements. / Kok, C. K.; Chew, Weng Cho; Chim, W. K. et al.
1999. 200-205 Paper presented at Proceedings of the 1999 7th International Symposium on Physical and Failure Analysis of Integrated Circuits, Singapore, Singapore.

Research output: Contribution to conference › Paper › peer-review

Kok, CK, Chew, WC, Chim, WK, Chan, DSH & Leang, SE 1999, 'Comparative study of charge trapping effects in LDD surface-channel and buried-channel PMOS transistors using charge profiling and threshold voltage shift measurements', Paper presented at Proceedings of the 1999 7th International Symposium on Physical and Failure Analysis of Integrated Circuits, Singapore, Singapore, 7/5/99 - 7/9/99 pp. 200-205.

Kok CK, Chew WC, Chim WK, Chan DSH, Leang SE. Comparative study of charge trapping effects in LDD surface-channel and buried-channel PMOS transistors using charge profiling and threshold voltage shift measurements. 1999. Paper presented at Proceedings of the 1999 7th International Symposium on Physical and Failure Analysis of Integrated Circuits, Singapore, Singapore.

Kok, C. K. ; Chew, Weng Cho ; Chim, W. K. et al. / Comparative study of charge trapping effects in LDD surface-channel and buried-channel PMOS transistors using charge profiling and threshold voltage shift measurements. Paper presented at Proceedings of the 1999 7th International Symposium on Physical and Failure Analysis of Integrated Circuits, Singapore, Singapore.6 p.

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abstract = "Extracted charge profiles of lightly-doped drain (LDD) surface-channel and buried-channel pMOS devices stressed under hot-carrier injection conditions reveal predominant electron trapping near the gate edge at the drain region in both cases. From threshold voltage measurements, there is some evidence of hole trapping after long stress times in surface-channel pMOSFETs, but not in buried-channel devices. Hot-electron trapping is the dominant degradation mechanism in buried-channel LDD pMOSFETs. For surface-channel LDD pMOSFETs, large concentrations of electron traps near the gate edge were found.",

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year = "1999",

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AU - Kok, C. K.

AU - Chew, Weng Cho

AU - Chim, W. K.

AU - Chan, D. S.H.

AU - Leang, S. E.

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Y1 - 1999

N2 - Extracted charge profiles of lightly-doped drain (LDD) surface-channel and buried-channel pMOS devices stressed under hot-carrier injection conditions reveal predominant electron trapping near the gate edge at the drain region in both cases. From threshold voltage measurements, there is some evidence of hole trapping after long stress times in surface-channel pMOSFETs, but not in buried-channel devices. Hot-electron trapping is the dominant degradation mechanism in buried-channel LDD pMOSFETs. For surface-channel LDD pMOSFETs, large concentrations of electron traps near the gate edge were found.

AB - Extracted charge profiles of lightly-doped drain (LDD) surface-channel and buried-channel pMOS devices stressed under hot-carrier injection conditions reveal predominant electron trapping near the gate edge at the drain region in both cases. From threshold voltage measurements, there is some evidence of hole trapping after long stress times in surface-channel pMOSFETs, but not in buried-channel devices. Hot-electron trapping is the dominant degradation mechanism in buried-channel LDD pMOSFETs. For surface-channel LDD pMOSFETs, large concentrations of electron traps near the gate edge were found.

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Comparative study of charge trapping effects in LDD surface-channel and buried-channel PMOS transistors using charge profiling and threshold voltage shift measurements

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