Comparative study of charge trapping effects in LDD surface-channel and buried-channel PMOS transistors using charge profiling and threshold voltage shift measurements

C. K. Kok, Weng Cho Chew, W. K. Chim, D. S.H. Chan, S. E. Leang

Research output: Contribution to conferencePaper

Abstract

Extracted charge profiles of lightly-doped drain (LDD) surface-channel and buried-channel pMOS devices stressed under hot-carrier injection conditions reveal predominant electron trapping near the gate edge at the drain region in both cases. From threshold voltage measurements, there is some evidence of hole trapping after long stress times in surface-channel pMOSFETs, but not in buried-channel devices. Hot-electron trapping is the dominant degradation mechanism in buried-channel LDD pMOSFETs. For surface-channel LDD pMOSFETs, large concentrations of electron traps near the gate edge were found.

Original languageEnglish (US)
Pages200-205
Number of pages6
StatePublished - Dec 1 1999
EventProceedings of the 1999 7th International Symposium on Physical and Failure Analysis of Integrated Circuits - Singapore, Singapore
Duration: Jul 5 1999Jul 9 1999

Other

OtherProceedings of the 1999 7th International Symposium on Physical and Failure Analysis of Integrated Circuits
CitySingapore, Singapore
Period7/5/997/9/99

ASJC Scopus subject areas

  • Engineering(all)

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    Kok, C. K., Chew, W. C., Chim, W. K., Chan, D. S. H., & Leang, S. E. (1999). Comparative study of charge trapping effects in LDD surface-channel and buried-channel PMOS transistors using charge profiling and threshold voltage shift measurements. 200-205. Paper presented at Proceedings of the 1999 7th International Symposium on Physical and Failure Analysis of Integrated Circuits, Singapore, Singapore, .