Compacted channel routing with via placement restrictions

D. F. Wong, C. L. Liu

Research output: Contribution to journalArticlepeer-review


We study in this paper the channel routing problem when there are restrictions on the placement of via holes. We show how to produce routing solutions that contain no horizontally adjacent vias and a close to minimum number of vertically and diagonally adjacent vias. Such solutions lead to compaction that will reduce total routing area.

Original languageEnglish (US)
Pages (from-to)287-307
Number of pages21
JournalIntegration, the VLSI Journal
Issue number4
StatePublished - Dec 1986


  • Channel routing
  • compaction
  • vias

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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