Abstract
We study in this paper the channel routing problem when there are restrictions on the placement of via holes. We show how to produce routing solutions that contain no horizontally adjacent vias and a close to minimum number of vertically and diagonally adjacent vias. Such solutions lead to compaction that will reduce total routing area.
Original language | English (US) |
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Pages (from-to) | 287-307 |
Number of pages | 21 |
Journal | Integration, the VLSI Journal |
Volume | 4 |
Issue number | 4 |
DOIs | |
State | Published - Dec 1986 |
Keywords
- Channel routing
- compaction
- vias
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering