Compact modeling of vertical ESD protection NPN transistors for RF circuits

Sopan Joshi, Elyse Rosenbaum

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We present an easy-to-use, simulator-independent compact model of a vertical npn transistor suitable for ESD circuit simulation. In addition to including high-current and breakdown effects, we also model accurately the small-signal off-state impedance of the device using s-parameter measurements, for inclusion in RF circuit simulations. Experimental results are provided for silicon and SiGe npn transistors.

Original languageEnglish (US)
Title of host publicationElectrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2002 - Proceedings
PublisherESD Association
Pages292-298
Number of pages7
ISBN (Electronic)1585370401, 9781585370405
StatePublished - 2002
Event24th Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2002 - Charlotte, United States
Duration: Oct 6 2002Oct 10 2002

Publication series

NameElectrical Overstress/Electrostatic Discharge Symposium Proceedings
Volume2002-January
ISSN (Print)0739-5159

Other

Other24th Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2002
Country/TerritoryUnited States
CityCharlotte
Period10/6/0210/10/02

Keywords

  • Circuit simulation
  • Computational modeling
  • Computer simulation
  • Electric breakdown
  • Electrostatic discharge
  • Hardware design languages
  • Impedance
  • Protection
  • Radio frequency
  • Virtual colonoscopy

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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