Compact modeling of on-chip ESD protection devices using Verilog-A

Junjun Li; Sopan Joshi; Ryan Barnes; Elyse Rosenbaum

doi:10.1109/tcad.2005.855948

Compact modeling of on-chip ESD protection devices using Verilog-A

Junjun Li, Sopan Joshi, Ryan Barnes, Elyse Rosenbaum

Research output: Contribution to journal › Article

Abstract

A practical approach for the compact modeling of electrostatic discharge (ESD) protection devices, using the behavioral language Verilog-A, is presented. Models of the NMOS transistor, the vertical n-p-n transistor, the diode, and the resistor have been developed, suitable for circuit-level simulation. Large-signal and small-signal models are provided for transient and alternating current (ac) simulation, respectively. A self-heating model is included for accurate simulation of the device ON-resistance under transient high-current conditions.

Original language	English (US)
Pages (from-to)	1047-1063
Number of pages	17
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	25
Issue number	6
DOIs	https://doi.org/10.1109/tcad.2005.855948
State	Published - Jun 2006

Keywords

Electrostatic discharge (ESD)
Metal-oxide-semiconductor (MOS) model
Reliability
Verilog-A

ASJC Scopus subject areas

Software
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

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abstract = "A practical approach for the compact modeling of electrostatic discharge (ESD) protection devices, using the behavioral language Verilog-A, is presented. Models of the NMOS transistor, the vertical n-p-n transistor, the diode, and the resistor have been developed, suitable for circuit-level simulation. Large-signal and small-signal models are provided for transient and alternating current (ac) simulation, respectively. A self-heating model is included for accurate simulation of the device ON-resistance under transient high-current conditions.",

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