Compact modeling of on-chip ESD protection devices using Verilog-A

Junjun Li, Sopan Joshi, Ryan Barnes, Elyse Rosenbaum

Research output: Contribution to journalArticle

Abstract

A practical approach for the compact modeling of electrostatic discharge (ESD) protection devices, using the behavioral language Verilog-A, is presented. Models of the NMOS transistor, the vertical n-p-n transistor, the diode, and the resistor have been developed, suitable for circuit-level simulation. Large-signal and small-signal models are provided for transient and alternating current (ac) simulation, respectively. A self-heating model is included for accurate simulation of the device ON-resistance under transient high-current conditions.

Original languageEnglish (US)
Pages (from-to)1047-1063
Number of pages17
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume25
Issue number6
DOIs
StatePublished - Jun 1 2006

Fingerprint

Computer hardware description languages
Electrostatic discharge
Transistors
Resistors
Diodes
Heating
Networks (circuits)

Keywords

  • Electrostatic discharge (ESD)
  • Metal-oxide-semiconductor (MOS) model
  • Reliability
  • Verilog-A

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

Compact modeling of on-chip ESD protection devices using Verilog-A. / Li, Junjun; Joshi, Sopan; Barnes, Ryan; Rosenbaum, Elyse.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 6, 01.06.2006, p. 1047-1063.

Research output: Contribution to journalArticle

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