Communicating novel computational state variables: Post-CMOS logic

The semiconducting material silicon forms the heart of the current complimentary metal-oxide semiconductor (CMOS) technology. Over the last four decades, the productivity of silicon technology has increased by a factor of more than a billion [1]. This growth in silicon technology was made possible by a steady reduction in the feature size, which helps pack more functionality per cost in a microprocessor. Today, the silicon-based semiconductor industry is an approximately US$270 billion market [1]. This exponential growth of the semiconductor industry was first observed by Dr. Gordon Moore. In 1965, Moore observed that the computing power of a microprocessor doubled every 18-24 months, and this observation later became known as Moore's law [2]. In essence, Moore's law is an economic law that serves to guide long-term planning and to set targets for research and development in the semiconductor industry. However, quantum-mechanical laws dictate that there are fundamental challenges associated with scaling on-chip components to below 10 nm [3]. A revolutionary innovation in semiconductor technology would be needed to sustain Moore's law for advanced technology nodes below 10 nm [1], [4]. We examine performance trends of on-chip devices and interconnects upon dimensional scaling. This is followed by a discussion on emerging technologies and the repercussions of interconnects for these novel technologies.