Combining trace sampling with single pass methods for efficient cache simulation

Thomas M. Conte, Mary Ann Hirsch, Wen Mei W. Hwu

Research output: Contribution to journalArticle

Abstract

The design of the memory hierarchy is crucial to the performance of high performance computer systems. The incorporation of multiple levels of caches into the memory hierarchy is known to increase the performance of high end machines, but the development of architectural prototypes of various memory hierarchy designs is costly and time consuming. In this paper, we will describe a single pass method used in combination with trace sampling techniques to produce a fast and accurate approach for simulating multiple sizes of caches simultaneously.

Original languageEnglish (US)
Pages (from-to)714-719
Number of pages6
JournalIEEE Transactions on Computers
Volume47
Issue number6
DOIs
StatePublished - Dec 1 1998

Fingerprint

Memory Hierarchy
Cache
Trace
Sampling
Data storage equipment
Simulation
Computer systems
High Performance
Prototype
Design

Keywords

  • Performance analysis
  • Sampling techniques
  • Single pass algorithms
  • Stacking algorithms
  • Trace-driven simulation

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

Cite this

Combining trace sampling with single pass methods for efficient cache simulation. / Conte, Thomas M.; Hirsch, Mary Ann; Hwu, Wen Mei W.

In: IEEE Transactions on Computers, Vol. 47, No. 6, 01.12.1998, p. 714-719.

Research output: Contribution to journalArticle

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