Abstract
In this paper, we present a coding framework derived from a communication-theoretic view of a DSM bus to jointly address power, delay, and reliability. In this framework, the data is first passed through a nonlinear source coder that reduces self and coupling transition activity and imposes a constraint on the peak coupling transitions on the bus. Next, a linear error control coder adds redundancy to enable error detection and correction. The framework is employed to efficiently combine existing codes and to derive novel codes that span a wide range of trade-offs between bus delay, codec latency, power, area, and reliability. Simulation results, for a 1-cm 32-bit bus in a 0.18-μm CMOS technology, show that 31% reduction in energy and 62% reduction in energy-delay product are achievable.
Original language | English (US) |
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Pages (from-to) | 103-106 |
Number of pages | 4 |
Journal | Proceedings - Design Automation Conference |
DOIs | |
State | Published - 2004 |
Event | Proceedings of the 41st Design Automation Conference - San Diego, CA, United States Duration: Jun 7 2004 → Jun 11 2004 |
Keywords
- Bus coding
- Crosstalk avoidance
- Error-correcting Codes
- Low-power
- Low-swing
ASJC Scopus subject areas
- Hardware and Architecture
- Control and Systems Engineering