Coding for system-on-chip networks: A unified framework

Srinivasa R. Sridhara, Naresh R Shanbhag

Research output: Contribution to journalConference article

Abstract

In this paper, we present a coding framework derived from a communication-theoretic view of a DSM bus to jointly address power, delay, and reliability. In this framework, the data is first passed through a nonlinear source coder that reduces self and coupling transition activity and imposes a constraint on the peak coupling transitions on the bus. Next, a linear error control coder adds redundancy to enable error detection and correction. The framework is employed to efficiently combine existing codes and to derive novel codes that span a wide range of trade-offs between bus delay, codec latency, power, area, and reliability. Simulation results, for a 1-cm 32-bit bus in a 0.18-μm CMOS technology, show that 31% reduction in energy and 62% reduction in energy-delay product are achievable.

Original languageEnglish (US)
Pages (from-to)103-106
Number of pages4
JournalProceedings - Design Automation Conference
StatePublished - Sep 20 2004
EventProceedings of the 41st Design Automation Conference - San Diego, CA, United States
Duration: Jun 7 2004Jun 11 2004

Fingerprint

Error detection
Error correction
Redundancy
System-on-chip
Communication

Keywords

  • Bus coding
  • Crosstalk avoidance
  • Error-correcting Codes
  • Low-power
  • Low-swing

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

Cite this

Coding for system-on-chip networks : A unified framework. / Sridhara, Srinivasa R.; Shanbhag, Naresh R.

In: Proceedings - Design Automation Conference, 20.09.2004, p. 103-106.

Research output: Contribution to journalConference article

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