Coding for system-on-chip networks: A unified framework

Srinivasa R. Sridhara, Naresh R. Shanbhag

Research output: Contribution to journalArticle

Abstract

Global buses in deep-submicron (DSM) system-on-chip designs consume significant amounts of power, have large propagation delays, and are susceptible to errors due to DSM noise. Coding schemes exist that tackle these problems individually. In this paper, we present a coding framework derived from a communication-theoretic view of a DSM bus to jointly address power, delay, and reliability. In this framework, the data is first passed through a nonlinear source coder that reduces self and coupling transition activity and imposes a constraint on the peak coupling transitions on the bus. Next, a linear error control coder adds redundancy to enable error detection and correction. The framework is employed to efficiently combine existing codes and to derive novel codes that span a wide range of tradeoffs between bus delay, codec latency, power, area, and reliability. Using simulation results in 0.13-μm CMOS technology, we show that coding is a better alternative to repeater insertion for delay reduction as it reduces power dissipation at the same time. For a 10-mm 4-bit bus, we show that a bus employing the proposed codes achieves up to 2.17 × speed-up and 33% energy savings over a bus employing Hamming code. For a 10-mm 32-bit bus, we show that 1.7 × speed-up and 27% reduction in energy are achievable over an uncoded bus by employing low-swing signaling without any loss in reliability.

Original languageEnglish (US)
Pages (from-to)655-667
Number of pages13
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume13
Issue number6
DOIs
StatePublished - Jun 1 2005

Keywords

  • Bus coding
  • Bus delay
  • Crosstalk avoidance
  • Interconnection networks
  • Low-power
  • On-chip buses
  • Reliability
  • System-on-chip

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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