Coding for reliable on-chip buses: Fundamental limits and practical codes

Srinivasa R. Sridhara, Naresh R. Shanbhag

Research output: Contribution to journalConference articlepeer-review


A reliable high-speed bus employing low-swing signaling can be designed by encoding the bus to prevent crosstalk and provide error correction. In this paper, we present fundamental limits on the number of wires required to achieve joint crosstalk avoidance and error correction in on-chip buses. We propose a code construction that results in practical encoding and decoding schemes with the number of wires being within 35% of the fundamental limits. The proposed codes, when applied to a 10-mm 32-bit bus in a 0.13-μm CMOS technology with low-swing signaling, provide 2.14 × speed-up and 27.5% energy savings without any loss in reliability.

Original languageEnglish (US)
Pages (from-to)417-422
Number of pages6
JournalProceedings of the IEEE International Conference on VLSI Design
StatePublished - 2005
Event18th International Conference on VLSI Design: Power Aware Design of VLSI Systems - Kolkata, India
Duration: Jan 3 2005Jan 7 2005

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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