Coding for reliable on-chip buses: A class of fundamental bounds and practical codes

Srinivasa R. Sridhara, Naresh R. Shanbhag

Research output: Contribution to journalArticlepeer-review


A reliable high-speed bus employing low-swing signaling can be designed by encoding the bus to prevent crosstalk and provide error correction. Coding for on-chip buses requires additional bus wires and codec circuits. In this paper, fundamental bounds on the number of wires required to provide joint crosstalk avoidance and error correction using memoryless codes are presented. The authors propose a code construction that results in practical codec circuits with the number of wires being within 35% of the fundamental bounds. When applied to a 10-mm 32-bit bus in a 0.13-μm CMOS technology with low-swing signaling, one of the proposed codes provides 2.14X speedup and 27.5% energy savings at the cost of 2.1X area overhead, but without any loss in reliability.

Original languageEnglish (US)
Pages (from-to)977-982
Number of pages6
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number5
StatePublished - May 2007


  • Coding
  • Crosstalk
  • Error correction
  • Interconnect
  • Low power
  • On-chip bus
  • Reliability

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


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