TY - GEN
T1 - CODIC
T2 - 48th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2021
AU - Orosa, Lois
AU - Wang, Yaohua
AU - Sadrosadati, Mohammad
AU - Kim, Jeremie S.
AU - Patel, Minesh
AU - Puddu, Ivan
AU - Luo, Haocong
AU - Razavi, Kaveh
AU - Gomez-Luna, Juan
AU - Hassan, Hasan
AU - Mansouri-Ghiasi, Nika
AU - Ghose, Saugata
AU - Mutlu, Onur
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021/6
Y1 - 2021/6
N2 - DRAM is the dominant main memory technology used in modern computing systems. Computing systems implement a memory controller that interfaces with DRAM via DRAM commands. DRAM executes the given commands using internal components (e.g., access transistors, sense amplifiers) that are orchestrated by DRAM internal timings, which are fixed for each DRAM command. Unfortunately, the use of fixed internal timings limits the types of operations that DRAM can perform and hinders the implementation of new functionalities and custom mechanisms that improve DRAM reliability, performance and energy. To overcome these limitations, we propose enabling programmable DRAM internal timings for controlling in-DRAM components.To this end, we design CODIC, a new low-cost DRAM substrate that enables fine-grained control over four previously fixed internal DRAM timings that are key to many DRAM operations. We implement CODIC with only minimal changes to the DRAM chip and the DDRx interface. To demonstrate the potential of CODIC, we propose two new CODIC-based security mechanisms that outperform state-of-the-art mechanisms in several ways: (1) a new DRAM Physical Unclonable Function (PUF) that is more robust and has significantly higher throughput than state-of-the-art DRAM PUFs, and (2) the first cold boot attack prevention mechanism that does not introduce any performance or energy overheads at runtime.
AB - DRAM is the dominant main memory technology used in modern computing systems. Computing systems implement a memory controller that interfaces with DRAM via DRAM commands. DRAM executes the given commands using internal components (e.g., access transistors, sense amplifiers) that are orchestrated by DRAM internal timings, which are fixed for each DRAM command. Unfortunately, the use of fixed internal timings limits the types of operations that DRAM can perform and hinders the implementation of new functionalities and custom mechanisms that improve DRAM reliability, performance and energy. To overcome these limitations, we propose enabling programmable DRAM internal timings for controlling in-DRAM components.To this end, we design CODIC, a new low-cost DRAM substrate that enables fine-grained control over four previously fixed internal DRAM timings that are key to many DRAM operations. We implement CODIC with only minimal changes to the DRAM chip and the DDRx interface. To demonstrate the potential of CODIC, we propose two new CODIC-based security mechanisms that outperform state-of-the-art mechanisms in several ways: (1) a new DRAM Physical Unclonable Function (PUF) that is more robust and has significantly higher throughput than state-of-the-art DRAM PUFs, and (2) the first cold boot attack prevention mechanism that does not introduce any performance or energy overheads at runtime.
UR - http://www.scopus.com/inward/record.url?scp=85107775408&partnerID=8YFLogxK
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U2 - 10.1109/ISCA52012.2021.00045
DO - 10.1109/ISCA52012.2021.00045
M3 - Conference contribution
AN - SCOPUS:85107775408
T3 - Proceedings - International Symposium on Computer Architecture
SP - 484
EP - 497
BT - Proceedings - 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture, ISCA 2021
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 14 June 2021 through 19 June 2021
ER -