@inproceedings{508c45ba40ea48b1bf11bdb7ff321eef,
title = "Code coverage of assertions using RTL source code analysis",
abstract = "Assertions are gaining importance in pre-silicon hardware verification to ensure expected design behavior. Coverage of an assertion in terms of statements of a Register Transfer Level (RTL) source code is a very accessible metric for understanding the scope of assertions and for debug. However, few methods to report it currently exist. We present a methodology to define and compute code coverage of an assertion. Our method is based on static and dynamic analysis of the RTL source code. We demonstrate the scalability and effectiveness of our approach with experimental results on real designs for both manual and automatically generated assertions.",
keywords = "Assertions, Code coverage, Formal verification, Static analysis",
author = "Viraj Athavale and Sai Ma and Samuel Hertz and Shobha Vasudevan",
year = "2014",
doi = "10.1145/2593069.2593108",
language = "English (US)",
isbn = "9781479930173",
series = "Proceedings - Design Automation Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "DAC 2014 - 51st Design Automation Conference, Conference Proceedings",
address = "United States",
note = "51st Annual Design Automation Conference, DAC 2014 ; Conference date: 02-06-2014 Through 05-06-2014",
}