Code coverage of assertions using RTL source code analysis

Viraj Athavale, Sai Ma, Samuel Hertz, Shobha Vasudevan

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Assertions are gaining importance in pre-silicon hardware verification to ensure expected design behavior. Coverage of an assertion in terms of statements of a Register Transfer Level (RTL) source code is a very accessible metric for understanding the scope of assertions and for debug. However, few methods to report it currently exist. We present a methodology to define and compute code coverage of an assertion. Our method is based on static and dynamic analysis of the RTL source code. We demonstrate the scalability and effectiveness of our approach with experimental results on real designs for both manual and automatically generated assertions.

Original languageEnglish (US)
Title of host publicationDAC 2014 - 51st Design Automation Conference, Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781479930173
StatePublished - 2014
Externally publishedYes
Event51st Annual Design Automation Conference, DAC 2014 - San Francisco, CA, United States
Duration: Jun 2 2014Jun 5 2014

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X


Other51st Annual Design Automation Conference, DAC 2014
Country/TerritoryUnited States
CitySan Francisco, CA


  • Assertions
  • Code coverage
  • Formal verification
  • Static analysis

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation


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