TY - JOUR
T1 - CNFET-Based High Throughput SIMD Architecture
AU - Jiang, Li
AU - Li, Tianjian
AU - Jing, Naifeng
AU - Kim, Nam Sung
AU - Guo, Minyi
AU - Liang, Xiaoyao
N1 - Funding Information:
Manuscript received September 15, 2016; revised February 22, 2017; accepted March 21, 2017. Date of publication April 19, 2017; date of current version June 18, 2018. This work was supported in part by the National Natural Science Foundation of China under Grant 61602300, Grant 61332001, and Grant 61402285, in part by the Shanghai Science and Technology Committee under Grant 15YF1406000, in part by the U.S. NSF under Grant CNS-1217102, and in part by the Program of China National 1000 Young Talent Plan. This paper was recommended by Associate Editor F. Firouzi. (Corresponding author: Nam Sung Kim.) L. Jiang, T. Li, M. Guo, and X. Liang are with the Department of Computer Science and Engineering, Shanghai Jiao Tong University, Shanghai 200240, China (e-mail: jiangli@cs.sjtu.edu.cn).
Funding Information:
This work was supported in part by the National Natural Science Foundation of China under Grant 61602300, Grant 61332001, and Grant 61402285, in part by the Shanghai Science and Technology Committee under Grant 15YF1406000, in part by the U.S. NSF under Grant CNS-1217102, and in part by the Program of China National 1000 Young Talent Plan.
Publisher Copyright:
© 1982-2012 IEEE.
PY - 2018/7
Y1 - 2018/7
N2 - Carbon nanotube field effect transistor (CNFET), using the carbon nanotubes (CNTs) as the material for conducting, is a promising alternative of CMOS technology to overcome the 'power wall' issue. Recently, a microprocessor solely based on CNFETs was fabricated and demonstrated, which is a big step forward to the industrial practice. However, CNFETs are inherently subject to much larger process variation or manufacturing defects; thereby it may cause significant design cost to build high performance processors. This is exacerbated in the large register file (RF) architectures widely used in single instruction multiple data (SIMD) architectures, e.g., general public utilities style processors, where the number of critical paths are multiplied by the SIMD width and thread count. In this paper, we seek cost-effective approaches to address the issues by judiciously exploiting the strong asymmetric spatial correlation in the variation unique to the CNFET fabrication process. This paper presents a microarchitectural model to characterize CNFET delay variation and malfunction, under which we show that the RF organizations coupled with the architectural schemes are critical to the performance and power consumption of the SIMD processor. Therefore, we propose several architectural techniques to mitigate the performance degradation and the impact of CNT metallization, leveraging the distinctive CNFET characteristics and the unique features in the SIMD processors. Experimental results verify the effectiveness of the proposed techniques and demonstrate the great opportunity offered by this new device technology.
AB - Carbon nanotube field effect transistor (CNFET), using the carbon nanotubes (CNTs) as the material for conducting, is a promising alternative of CMOS technology to overcome the 'power wall' issue. Recently, a microprocessor solely based on CNFETs was fabricated and demonstrated, which is a big step forward to the industrial practice. However, CNFETs are inherently subject to much larger process variation or manufacturing defects; thereby it may cause significant design cost to build high performance processors. This is exacerbated in the large register file (RF) architectures widely used in single instruction multiple data (SIMD) architectures, e.g., general public utilities style processors, where the number of critical paths are multiplied by the SIMD width and thread count. In this paper, we seek cost-effective approaches to address the issues by judiciously exploiting the strong asymmetric spatial correlation in the variation unique to the CNFET fabrication process. This paper presents a microarchitectural model to characterize CNFET delay variation and malfunction, under which we show that the RF organizations coupled with the architectural schemes are critical to the performance and power consumption of the SIMD processor. Therefore, we propose several architectural techniques to mitigate the performance degradation and the impact of CNT metallization, leveraging the distinctive CNFET characteristics and the unique features in the SIMD processors. Experimental results verify the effectiveness of the proposed techniques and demonstrate the great opportunity offered by this new device technology.
KW - Asymmetric spatial correlation
KW - carbon nanotube field effect transistor (CNFET)
KW - register file (RF) architecture
KW - single instruction multiple data (SIMD) processor
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U2 - 10.1109/TCAD.2017.2695899
DO - 10.1109/TCAD.2017.2695899
M3 - Article
AN - SCOPUS:85048801580
VL - 37
SP - 1331
EP - 1344
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SN - 0278-0070
IS - 7
ER -