CMOS Skewed Static Logic And Method Of Synthesis

A new CMOS skewed static logic gate is provided having a logic function circuit and a positive feedback or accelerator circuit. The skewed gate uses a plurality of transistors matched and joined as a plurality of separate gate inputs to form the logic function circuit and the accelerator circuit. The accelerator circuit, which connects to an output of the logic function circuit, provides acceleration to the evaluation performed by the logic function circuit. The logic function circuit includes an evaluation path connected to a set of output transistors that connect to transistors of the accelerator circuit. The evaluation path includes a stacked set of low threshold voltage (Vt) transistors, which have a lower Vt than the set of output transistors. The output transistors are configured to receive a first input signal to precharge an output of the CMOS skewed static logic gate prior to the skewed gate receiving a second input signal.