Clustering and load balancing for buffered clock tree synthesis

Ashish D. Mehta, Yao Ping Chen, Noel Menezes, D. F. Wong, Lawrence T. Pileggi

Research output: Contribution to conferencePaperpeer-review


Buffers in clock trees introduce two additional sources of skew: The first source of skew is the effect of process variations on buffer delays. The second source of skew is the imbalance in buffer loading. We propose a buffered clock tree synthesis methodology whereby we first apply a clustering algorithm to obtain clusters of approximately equal capacitance loading. We drive each of these clusters with identical buffers. A sensitivity based approach is then used for equalizing the Elmore delay from the buffer output to all of the clock nodes. The skew due to load imbalance is minimized concurrently by matching a higher-order model of the load by wire sizing and wire lengthening. We demonstrate how this algorithm can be used recursively to generate low-skew buffered clock trees.

Original languageEnglish (US)
Number of pages7
StatePublished - 1997
Externally publishedYes
EventProceedings of the 1997 International Conference on Computer Design - Austin, TX, USA
Duration: Oct 12 1997Oct 15 1997


OtherProceedings of the 1997 International Conference on Computer Design
CityAustin, TX, USA

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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