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Closed form solution to simultaneous buffer insertion/sizing and wire sizing
C. Chu
,
D. F. Wong
Research output
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peer-review
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Keyphrases
Buffer Insertion
100%
Buffer Sizing
33%
Delay Minimization
33%
Design Performance
33%
Floorplanning
33%
General Terms
33%
Interconnect Wire
33%
Logic Synthesis
33%
Minimization Problem
33%
No-buffer
33%
Optimal number
33%
Performance Theory
33%
VLSI Design Flow
33%
Wire Sizing
100%
Engineering
Closed Form
50%
Closed Form Solution
100%
Design Flow
50%
Early Stage
50%
Interconnects
50%
Logic Synthesis
50%
Minimization Problem
50%
Term Design
50%
Computer Science
Buffer Insertion
100%
Delay Minimization
50%
Floorplanning
50%
Logic Synthesis
50%
Minimization Problem
50%
Nursing and Health Professions
Buffer
100%