TY - JOUR
T1 - Clocked magnetostriction-assisted spintronic device design and simulation
AU - Mousavi Iraei, Rouhollah
AU - Kani, Nickvash
AU - Dutta, Sourav
AU - Nikonov, Dmitri E.
AU - Manipatruni, Sasikanth
AU - Young, Ian A.
AU - Heron, John T.
AU - Naeemi, Azad
N1 - Funding Information:
Manuscript received February 21, 2018; revised March 12, 2018; accepted March 16, 2018. Date of publication April 4, 2018; date of current version April 20, 2018. This work was supported by the Semiconductor Research Corporation through the research program MSR-Intel with research task/theme ID spin interconnects under Grant 2616.001. The review of this paper was arranged by Editor C. Monzio Compagnoni. (Corresponding author: Rouhollah Mousavi Iraei.) R. Mousavi Iraei, N. Kani, S. Dutta, and A. Naeemi are with the Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332 USA (e-mail: iraei@gatech.edu).
Publisher Copyright:
© 1963-2012 IEEE.
PY - 2018/5
Y1 - 2018/5
N2 - We propose a heterostructure device comprised of magnets and piezoelectrics, which significantly improves the delay and the energy dissipation of an all-spin logic (ASL) device. This paper studies and models the physics of the device, illustrates its operation, and benchmarks its performance using SPICE simulations. We show that the proposed device maintains low-voltage operation, nonreciprocity, nonvolatility, cascadability, and thermal reliability of the original ASL device. Moreover, by utilizing the deterministic switching of a magnet from the saddle point of the energy profile, the device is more efficient in terms of energy and delay and is robust to thermal fluctuations. The results of simulations show that compared to ASL devices, the proposed device achieves 21\times shorter delay and 27\times lower energy dissipation per bit for a 32-bit arithmetic-logic unit.
AB - We propose a heterostructure device comprised of magnets and piezoelectrics, which significantly improves the delay and the energy dissipation of an all-spin logic (ASL) device. This paper studies and models the physics of the device, illustrates its operation, and benchmarks its performance using SPICE simulations. We show that the proposed device maintains low-voltage operation, nonreciprocity, nonvolatility, cascadability, and thermal reliability of the original ASL device. Moreover, by utilizing the deterministic switching of a magnet from the saddle point of the energy profile, the device is more efficient in terms of energy and delay and is robust to thermal fluctuations. The results of simulations show that compared to ASL devices, the proposed device achieves 21\times shorter delay and 27\times lower energy dissipation per bit for a 32-bit arithmetic-logic unit.
KW - 32-Bit arithmetic-logic unit (ALU)
KW - All-spin logic (ASL)
KW - Interconnect
KW - Magnetostriction
KW - Magnets
KW - Piezoelectrics
KW - Spin-transfer torque (STT)
KW - Thermal noise
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U2 - 10.1109/TED.2018.2817556
DO - 10.1109/TED.2018.2817556
M3 - Article
AN - SCOPUS:85045193123
SN - 0018-9383
VL - 65
SP - 2040
EP - 2046
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 5
ER -