Clock tree synthesis under aggressive buffer insertion

Ying Yu Chen, Chen Dong, Deming Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we propose a maze-routing-based clock tree routing algorithm integrated with buffer insertion, buffer sizing and topology generation that is able to consider general buffer insertion locations in order to achieve robust slew control. Buffer insertion along routing paths had been mostly avoided previously due to the difficulty to maintain low skew under such aggressive buffer insertion. We develop accurate timing analysis engine for delay and slew estimation and a balanced routing scheme for better skew reduction during clock tree synthesis. As a result, we can perform aggressive buffer insertion with buffer sizing and maintain accurate delay information and low skew. Experiments show that our synthesis results not only honor the hard slew constraints but also maintain reasonable skew.

Original languageEnglish (US)
Title of host publicationProceedings of the 47th Design Automation Conference, DAC '10
Pages86-89
Number of pages4
DOIs
StatePublished - Sep 7 2010
Event47th Design Automation Conference, DAC '10 - Anaheim, CA, United States
Duration: Jun 13 2010Jun 18 2010

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Other

Other47th Design Automation Conference, DAC '10
CountryUnited States
CityAnaheim, CA
Period6/13/106/18/10

Keywords

  • Buffer insertion
  • Buffer sizing
  • Clock tree
  • Maze routing
  • Slew

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

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