Classifier circuits with graphene transistors

Wenjuan Zhu (Inventor), Jialun Liu (Inventor), Hojoon Ryu (Inventor)

Research output: Patent


A classifier circuit includes an array of dual gate graphene transistors, each of the transistors having a source, a top gate receiving one of an input voltage to be evaluated or a reference voltage, a bottom or embedded gate receiving the other of the input voltage or reference voltage and a drain, the source and drain contacting a graphene channel One of the source and the drain is connected to a voltage source. A common output combines output current of a plurality of the dual gate graphene transistors, which current varies in response to the difference between the input voltage and the reference voltage. A method for forming a classifier transistor with high remanent polarization forms dielectric with ferroelectric capability on a low resistivity substrate. A non-ferroelectric oxide layer is formed on the dielectric. A window is opened, and a graphene channel is formed in the window.
Original languageEnglish (US)
U.S. patent number11239320
Filing date12/6/19
StatePublished - Feb 1 2022


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